1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device and more particularly to a method of forming a capacitor.
1. Description of the Prior Art
In a typical dynamic memory device available today, each memory cell comprises one storage capacitor and one insulated gate field effect transistor (MOSFET). This capacitor stores information in the form of electric charges, while the transistor functions as a transfer gate between the capacitor and a bit line. To surely determine whether the capacitor is holding electric charges and reduce the soft error rate, the capacitance C of the capacitor is preferably as large as possible. The capacitance of a capacitor is expressed as C=.epsilon.s/t, where .epsilon. is the dielectric constant of the insulation layer, s is the capacitor electrode area, and t is the thickness of the insulation layer.
On the other hand, for a high integration of the memory device, it is desirable to reduce the planar area which the capacitor occupies on a semiconductor chip. For assuring a sufficient value of capacitance C with a decreased capacitor electrode area s, it might be contemplated to reduce the thickness t of the insulation layer. However, the requirement of reliable insulation naturally imposes a limitation on the thickness of the insulation layer.
Therefore, in order to provide a sufficient effective electrode area s with a decreased planar area, a trench type capacitor has been proposed. However, in view of the prolonged etching time required and in consideration of the durability of the etching mask, the depth of the trench is also subject to a certain limitation. Therefore, a trench capacitor having a plurality of hollows in the side wall of the trench and a method of manufacturing it has recently been described in Japanese Patent Laying-Open Gazette No. 173871/1985.
FIG. 4 is a vertical sectional view of the memory cell disclosed in this Japanese Patent Laying-Open Gazette No. 173871/1985. As shown, one transistor and one capacitor are formed in a region surrounded by an isolating oxide layer 2 on a P-type silicon substrate 1. The capacitor comprises a silicon oxide insulation film 4 and a polysilicon capacitor electrode 6. The transistor comprises an N-type source region 8a, an N-type drain region 8b, a polysilicon gate electrode 7a and a silicon oxide gate insulation film 5. The drain 8b is connected to a bit line (not shown) and the gate electrode 7a is connected to a word line 7b of, for example, aluminum through a contact hole opened in an insulation layer 9. Moreover, the capacitor includes a trench region and the side wall of this trench has a plurality of hollows 10. Therefore, this capacitor occupies only a small planar area on substrate 1 and yet has a large effective electrode area.
FIGS. 5A through 5L schematically illustrate the steps for creating such a capacitor.
Referring to FIG. 5A, a thick isolating oxide layer 2 is formed on a P-type silicon substrate by the conventional selective oxidation method. Thereafter, the surface of substrate 1 is covered with a silicon oxide film 3 formed by the thermal oxidation. Provided through the silicon oxide layer 3 by photoetching is an opening, through which a trench 11 is created into substrate 1 by anisotropic etching. This anisotropic etching may for example be reactive ion etching with CCl.sub.4 gas.
Referring, now, to FIG. 5B, an oxide film 4 is formed on the internal surface of said trench 11.
Referring to FIG. 5C, the oxide film 4 on the bottom surface of trench 11 is removed by anisotropic etching. This anisotropic etching may for example be reactive ion etching with CF.sub.4 +H.sub.2 gas.
Then, as illustrated in FIG. 5D, the bottom of trench 11 after removal of oxide film 4 is expanded by isotropic etching to form a lateral hollow or cavity 10. This isotropic etching may for example be plasma etching with CF.sub.4 +O.sub.2 gas.
Referring to FIG. 5E, the expanded bottom of trench 11 is covered with an oxide film 4.
Referring, now, to FIG. 5F, the trench 11 is deepened by anisotropic etching of its bottom.
Then, as illustrated in FIG. 5G, the internal surface of the new extension of trench 11 is covered with an oxide film 4.
Referring to FIG. 5H, the oxide film on the bottom of trench 11 is removed by anisotropic etching.
Referring to FIG. 5I, the bottom of trench 11 after removal of oxide film 4 is expanded by isotropic etching to form a second lateral hollow 10.
Then, as illustrated in FIG. 5J, the expanded bottom of trench 11 is covered with an oxide film 4.
The above sequence is repeated to form a third hollow 10 as illustrated in FIG. 5K.
Finally, the oxide film mask 3 is removed and the bottom of trench 11 and the top of substrate 1 are respectively covered with an oxide film 4. The above procedure gives a finished trench 11 having a plurality of hollows 10 along its side wall and having been covered with oxide film 4 as illustrated in FIG. 5L. Thereafter, the conventional procedure is followed to fabricate a memory cell having a trench type capacitor as shown in FIG. 4.